1. Field of the Invention
This invention relates to metal oxide semiconductor technology and in particular to AND-gate clocks.
2. Description of the Prior Art
The AND-ing of two or more inputs in a dynamic MOS clock circuit has been a particularly difficult problem, primarily because of the large transistor sizes involved and the high power dissipated before the clock is triggered. Previously, signals were ANDed in a dynamic clock as shown in FIG. 1. In this circuit the transistors T.sub.10 and T.sub.11 form an output stage wherein T.sub.10 is the driving transistor. In this circuit, the output .phi..sub.3 is conditional upon both .phi..sub.1 and .phi..sub.2 being high. The problems occur when .phi..sub.1 occurs earlier than .phi..sub.2, since the node N.sub.5 goes high while the Node N.sub.2 remains high. In order to prevent .phi..sub.3 from rising during this time, transistor T.sub.11 is typically much larger than the transistor T.sub.10. However, the driving transistor, T.sub.10, must be very large in order to handle the capacitance C.sub.L. Thus, T.sub.11 becomes very large, as much as approximately 700 microns in channel length for T.sub.10 =100 microns. Also, during the time that .phi..sub.2 remains low, a large amount of current flows through T.sub.10 and T.sub.11.